Georgia Tech and its partners have developed 2.5D glass interposer technology as a superior alternative to organic interposers in interconnect density, and silicon interposers in electrical performance, power consumption, and cost.

Georgia Tech was the first to start glass packaging five years ago as the next generation packaging technology after plastic or leadframe packaging in the 1970s, ceramic packaging in 1980s, and organic build-up in the 1990s. Georgia Tech proposed glass packaging as a superior packaging platform due to its improved electrical properties including low dielectric constant and low dielectric loss, thermal expansion match to silicon ICs, smooth surface finish, low moisture absorption, and availability in ultra-thin and large form factors without grinding. Georgia Tech identified and addressed three fundamental limitations of glass packaging that included low thermal conductivity, TSV-like through via formation at fine pitch and low cost, and mechanical brittleness.

Currently, Georgia Tech is designing and demonstrating glass packaging for a variety of applications including digital, RF, power, flexible electronics and automotive applications.

The goal of Georgia Tech’s 2.5D glass interposer is to serve high-performance computing markets including networks, graphics and as the interconnect platform for split SOCs, as announced by IBM, AMD and now Intel. These markets share a common set of system requirements—low latency, ultra-high interconnect density for ultra-high bandwidth, low-power interconnections, large package size, and low cost. Currently, silicon interposer is the only commercially-available technology that begins to address these system needs. Silicon interposers, while they provide suitable interconnect density, suffer from high signal losses due to dielectric and conductor losses and high cost due to small 300 mm size wafer processing and manufacturing, as well as the need for an organic BGA package between the interposer and system board. Organic interposers are being developed to overcome these limitations of silicon interposers, but are fundamentally limited in I/O density over the long term. Georgia Tech’s glass interposer, in contrast, is made up of 100 micron thin glass, which is available in large panel or roll-to-roll form, with through via at as low as 30 micron pitch and fine-pitch RDL with microvias at less than 10 microns—enabling 40 micron chip-level I/O pitch in development and 20 micron pitch in research.

Georgia Tech and its industry partners are designing and developing 2.5D glass interposer BGA packages with the following strategic advantages:

• High electrical performance achieved using low permittivity and low loss dielectrics to fabricate multilayer RDL wiring lines at 6 micron line pitch with 3 micron line lithography leading to 40 micron bump pitch, enabling short, high-density die-to-die interconnections with 0.12 dB/mm line insertion loss at 2 GHz.
• Low interconnect losses achieved by reducing dielectric and conductor losses using low loss dielectrics and thick copper conductive lines, compared to BEOL. As a result, line insertion losses for high-speed, off-package interconnects as low as 0.05 dB/mm are achieved—a 6X reduction compared to similar results reported with silicon interposers.
• High reliability using unique interposer fabrication and assembly technologies
• High density interconnections since glass behaves like silicon in its surface smoothness and dimensional stability in minimizing line lithography, line pitch and I/O pitch. The Georgia Tech program has recently demonstrated 3 micron wiring lines with via-in-pad technology at 40 micron I/O bump, targeting 20 micron pitch in 2016.

Direct board-level attachment of 2.5D glass interposer BGA: Unlike silicon interposer, which requires organic BGA for assembly to PCB, direct attachment of a glass interposer BGA to board has been demonstrated by the Georgia Tech team using a 18.5 mm glass BGA package size. The stresses due to CTE mismatch between the glass and board are managed by a variety of stress buffer approaches.

Cost: The cost of glass interposer package is expected to be similar to organic packages in high volume by utilizing large panels that are 5-10x larger than 300 mm silicon wafers. In addition to large panel processing to reduce cost, the Georgia Tech process uses low cost materials and dryfilm processes, double-side advanced semi-additive plating, large area lithography, high-speed plating, and panel scalable die assembly technologies.

The Georgia Tech glass packaging R&D is unique in the academic world. It involves partnership with manufacturing supply chain and end-user companies, resulting in accelerated 2.5D glass interposer package R&D. Corning and Asahi Glass, for example, have both developed high throughput roll-to-roll glass panel manufacturing as well as high throughput through-via processes and prepared them for volume manufacturing. Other supply chain manufacturing contributions to accelerate 2.5D fabrication development include: Ushio’s lithographic tool placed at Georgia Tech for 2 micron line lithography, SUSS MicroTec’s projection excimer laser ablation for microvias at less than 10 microns, Atotech’s differential seed layer etch for advanced SAP, as well as Shinko’s and Unimicron’s glass substrate prototype fabrication using panel manufacturing processes.

The current design and demonstration focus is the fabrication of low cost advanced RDL and TCB chip assembly processes, resulting in the first 2.5D glass interposer package prototype shown above.

The next focus is to apply this interposer technology for high bandwidth logic-to-memory applications working with semiconductor and system companies

For more information about Georgia Tech’s glass packaging technology, please contact Prof. Rao Tummala at rao.tummala@ece.gatech.edu.

About the Authors

Brett Sawyer, is a 4th year ECE student pursuing his PhD under the advisement of Prof. Rao Tummala. His research focus is on Modeling, Design, and Fabrication of 2.5D Glass Interposer. bsawyer@gatech.edu.

Dr. Rao Tummala is Director of Georgia Tech’s Packaging Research Center. He is also a Chaired Professor in ECE and MSE. rao.tummala@ece.gatech.edu.

Dr. Venky Sundaram is Program Manager for Glass Substrate at GT PRC and research faculty in ECE. vs24@mail.gatech.edu.