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Anvesha Amaravati Wins Best Paper Award
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Anvesha Amaravati won the Best Paper Award in the analog and mixed signal track at the 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2015). The conference was held October 5-7 in Daejon, Korea.
A Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE), Amaravati was honored for his paper entitled “A Time Interleaved DAC Sharing SAR Pipeline ADC for Ultra-Low Power Camera Front Ends." This paper presents a novel ADC architecture that can perform in-situ inner product on analog data with digital coefficients while enabling wide-input. The proposed design in 130nm CMOS process advances energy efficiency of the state-of-the-art designs by an order of magnitude and is particularly suited for low-power camera (and other sensor) front-ends.
Amaravati’s coauthors on this paper are Manan Chugh, an ECE graduate student, and Arijit Raychowdhury, who holds the ON Semiconductor Junior Professorship and who serves as Amaravati’s Ph.D. advisor.
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Summary
ECE Ph.D. student Anvesha Amaravati won the Best Paper Award in the analog and mixed signal track at the 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2015).
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- Workflow Status:Published
- Created By:Jackie Nemeth
- Created:10/22/2015
- Modified By:Fletcher Moore
- Modified:10/07/2016
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