Abstract : Transistor scaling is expected to soon reach its theoretical limits, diverging from Moores Law predictions and forcing the semiconductor industry to rethink its integration strategy beyond silicon. Packaging, until recently was treated as an afterthought, but now is seen as a key enabler to further increase functional densities, and meet the stringent performance and miniaturization requirements of emerging applications. A radical departure from existing roadmaps is now being pursued with the interconnect fabric paradigm, relying on the interconnection of functionally diverse dielets as micro-systems, and is expected to drive assembly pitches below 5µm, far beyond the fundamental limits of traditional solders. My vision for the evolution of off-chip interconnection and assembly technologies to meet the pitch scaling, increasing thermal, electrical, reliability and processing requirements of heterogeneous integration, with a focus on high-volume manufacturing, will be presented in the seminar. Both experimental and numerical modeling are necessary to make further progress, including: (1) incorporation of new solid-state joining and sintering methods relying on nanostructured nanoporous metals; (2) System reliability becomes more critical without a compliant layer such as solder to absorb thermal expansion stresses. A new research thrust is proposed to explore low-stress conductors such as Cu-graphene composites with novel manufacturing paths for their adoption as substrate metallization, Cu functionalization, or CTE-matched heat sinks for direct chip cooling. (3) Novel nanoscale joining techniques are also proposed as the next frontier for high-throughput, high-precision assembly. These breakthrough technologies will be illustrated in the light of two applications: HPC and power electronics, with a focus on reliability and condition monitoring as a new interdisciplinary and collaborative research pole to create at GT.

Biography: Dr. Vanessa Smet received her B.S. (2004) and M.S. (2007) in Applied Physics from the Ecole Normale Superieure and Paris XI University and her Ph.D. (2010) in Electronics from Montpellier University in France. She has taught undergraduate courses for 3 years at Montpelier University as part of the Agrégation in Applied Physics, a French National recruitment exam for teachers in college-level education. She was a post-doctoral research fellow with the Heterogeneous Integration group at Tyndall National Institute (Ireland) in 2010-2012. Since 2012, she has been affiliated with the 3D Systems Packaging Research Center (PRC) at Georgia Tech where she has been responsible for driving research efforts in two primary areas: 1) interconnections and assembly and 2) power electronics packaging. Her current research interests include low-cost synthesis of bulk nanocomposites of Cu-graphene as low-CTE conductors, nanoporous metals for smart assembly in next-gen heterogeneous systems as well as power electronics packaging, reliability and condition monitoring in self-driving cars. During her time at GT she has managed over $4M in research programs, over $2M of which she initiated as PI or Co-PI through PRC's industry Consortium, and external sponsors such as SRC and ARPA-E programs. She also established collaborations with several tool companies, resulting in the placement of a production-graded thermocompression tool at GT of a $1M value. She currently directly supervises 5 PhD and 1 MS student, and mentors 3 PhD students that are advised by PRC affiliated faculty. While at GT, Dr. Smet has lectured in the 6776 and 4755 classes, and has been a co-instructor of 4754 since 2013, teaching both lectures and labs in Spring 2019. All classes are ME/MSE/ECE cross-listed.

Refreshments will be provided at seminar.