This dissertation presents a multiscale modeling, optimization, and co-design framework for emerging memory technologies at advanced technology nodes, with a primary focus on spin-orbit-torque magnetic random-access memory (SOT-MRAM). A device-level framework is developed to capture nanoscale conduction-current redistribution and the resulting nonuniform spin-current generation in SOT devices, and is subsequently extended to compact two-terminal (2T) SOT-MRAM. For perpendicular-magnetic-anisotropy devices, full-fixed-layer and half-fixed-layer configurations are evaluated to quantify the effects of device geometry, MTJ scaling, and spin-torque efficiencies on write performance, demonstrating that the half-fixed-layer architecture can achieve competitive write energy with reduced out-of-plane spin-torque requirements. The shared read/write path of 2T SOT-MRAM is further investigated using a circuit-to-micromagnetics read-disturbance framework combining layout-extracted circuit simulations, finite-element current modeling, spin drift-diffusion analysis, and rare-event-enhancement-based micromagnetic simulations. The analysis is also extended to in-plane-magnetic-anisotropy devices using AuPt and β-W SOT channels, where the half-fixed-layer configuration reduces switching-current density and write energy. These device-level concepts are then incorporated into a hierarchical 2T SOT-MRAM system and evaluated after physical implementation, demonstrating substantial improvements in area, bit density, and read energy-delay-area product relative to a three-terminal baseline. Finally, advanced interconnect technologies are evaluated within a complete 7 nm SRAM RTL-to-GDS flow to establish an optimized conventional-memory reference, showing that BEOL improvements can significantly enhance SRAM performance and energy efficiency.