The objective of the proposed research is to explore digital-alike ADCs from the perspective of performance potential and automation potential. The first work presents an end-to-end automated VCO-based $\Delta \Sigma$ ADC generator. It exploits time-domain architectures so that the design can be generated on standard cell rather than transistor-level; thus, it speeds up and simplifies both the design phase and layout phase. Combined with an efficient knowledge-ML guided synthesis flow, it can translate input specifications to full system layout with reliable performance within minutes. This work also features a compact oscillator and system modeling method that facilitates light-resource accurate computation and network training. The generator is verified with 10 design cases in 65-nm and 28-nm processes, proving its capability of generating competitive design with good process portability. The second project introduces a high-precision third-order two-stage VCO-based ADC to investigate the potential of high-order VCO-based ADC. This design achieves enhanced resolution by extracting quantization noise from the first-stage VCO and directing it to the second-stage Time-to-Digital Converter (TDC). This innovative architecture not only addresses the non-linearity issues associated with VCO but also significantly reduces power consumption by employing a limited number of VCO stages. Additionally, the use of a gm-C as the first integrator contributes to substantial power savings. Moving forward, a fully synthesizable all-digital high-order VCO-based ADC will be designed.