The objective of the proposed research is to investigate scalable ferroelectric NAND (FE-NAND) memory architectures, with emphasis on device design and gate-stack engineering for memory-window (MW) optimization, retention, and pass-disturb reliability in silicon and oxide-semiconductor-channel devices. Gate stack engineering showed that Al2O3 dielectric is most effective as a tunnel dielectric layer (between two ferroelectric layers), while SiO2 performs best as a gate-blocking layer (between gate and ferroelectric layer). Combining both in a hybrid stack achieved an MW exceeding 11 V, highlighting the importance of dielectric material and placement. Channel-side interlayer studies further showed that SiO2 channel-IL provides approximately 15% higher MW, 5% lower retention loss, and 44% lower pass disturb than higher-k Al2O3 and HfO2, primarily due to reduced trap density. Finally, oxide-semiconductor-channel devices achieved approximately 1.5x larger MW than comparable silicon-channel devices but exhibited significant retention degradation from ambient oxygen interaction. Channel capping effectively suppressed this degradation and restored retention comparable to silicon devices, revealing an additional ambient-induced reliability mechanism unique to oxide-semiconductor FE-NAND