This dissertation presents scalable mixed-signal compute-in-memory architectures for solving integer-constrained least-squares problems. First, a fabricated 65-nm SRAM-based solver uses stochastic Hopfield dynamics to perform local optimization directly within memory. Next, a fabricated 28-nm analog compute-in-memory macro provides high-throughput vector–matrix multiplication, achieving 10.16 TOPS and a peak energy efficiency of 194.6 TOPS/W. Finally, these two hardware functions are integrated within a block-coordinate framework that decomposes large optimization problems into smaller subproblems. The results demonstrate how specialized compute-in-memory hardware can reduce data movement and provide an energy-efficient path toward solving larger integer-constrained optimization problems.