This thesis investigates mixed-signal compute-in-memory (CIM) architectures for energy- and area-efficient in-situ dimensionality reduction in radio-frequency (RF) sensing and communication systems. As wideband RF systems scale toward higher carrier frequencies and large antenna arrays, conventional digitize-everything architectures face prohibitive power, area, and data-movement overhead. To address this analog data deluge, this work develops analog compute-in-memory (ACIM) techniques that perform vector–matrix multiplication directly on analog sensor signals before digitization, reducing ADC count and downstream processing cost. The thesis presents SRAM-based current-domain ACIM macros, mixed-precision ACIM with digital feature restoration, cryogenic and Fe-FinFET-based ACIM designs for improved efficiency, and adaptive ACIM for subspace tracking in dynamic RF environments. Finally, a 256-element Slepian beamforming accelerator demonstrates the system-level feasibility of ACIM-based complex vector–matrix multiplication. Overall, this thesis shows that device–circuit–system co-designed mixed-signal CIM can provide a scalable and energy-efficient hardware path for next-generation RF signal processing systems.