The objective of the proposed research is to systematically investigate Die-to-Die (D2D) interfaces in chiplet-based systems across multiple packaging technologies, with a particular focus on the Universal Chiplet Interconnect Express (UCIe) standard. As heterogeneous integration becomes central to meeting the performance, bandwidth, and modularity demands of AI, HPC, and data-centric workloads, understanding how D2D signaling behavior varies across organic substrates, 2.5D interposers, 3D-ICE architectures, and emerging glass core substrates is critical. This research develops a unified modeling, simulation, and benchmarking framework that captures electrical performance on package- and system-level governing D2D performance. Preliminary work evaluates UCIe links in organic and 3D-ICE packages along with relative cost dynamics of UCIe-based chiplet-systems in 2D and 2.5D packaging technologies. The proposed work aims at extending these studies to glass substrates, perform design-space exploration across packaging technologies, assess via-region impacts, and include system-level architectural simulations. The final outcome aims to provide validated performance-cost tradeoffs, predictive machine-learning models, and design guidelines that enable standardized, high-performance, and scalable chiplet systems.