The objective of the proposed research is to (1) develop electronic design automation (EDA) tools for electromagnetic side-channel attack (EMSCA) security verification of cryptographic integrated circuits at the layout level and (2) design efficient and robust compute-in-memory circuit topologies for cryptographic algorithms. To address (1), this work proposes a pre-Silicon EMSCA simulation and verification framework which is used to perform a comprehensive IC layout study on an AES encryption engine in 65nm CMOS technology, demonstrating that a vast design optimization space exists wherein different layouts that all meet PPA requirements exhibit drastically varying vulnerability to EMSCA. To address (2), this work proposes AsconCIM, a novel compute-in-memory circuit topology which is used as a robust hardware implementation of the Ascon encryption and hashing algorithms, achieving a low-area, low-power, reliable and reconfigurable hardware implementation for Internet-of-Things (IoT) devices. Together, the proposed contributions establish a step forward for the next generation of verifiably secure, efficient, and robust cryptographic integrated circuits.