This dissertation presents a series of energy-efficient noise-shaping data converters that improve the performance, robustness, and integration of analog-to-digital interfaces. The proposed techniques address three major challenges in SAR ADCs—limited input driving capability, kT/C noise accumulation, and sensitivity to process, voltage, and temperature (PVT) variation. A third-order hybrid EF-CIFF SAR ADC achieves stable high-order noise shaping using a single dynamic amplifier with sampling noise cancellation. A fourth-order FIA-assisted EF-CRFF design integrates a noise-suppressed buffer-in-loop and kT/C noise cancellation for robust low-OSR operation. Finally, a two-step incremental ADC (IADC) with an inter-stage sub-ranging and GENS technique attains high resolution and energy efficiency with relaxed driver requirements. Together, these architectures establish a unified framework for high-order noise-shaping SAR-based converters, enabling compact, low-power, and PVT-robust analog front ends for next-generation sensing and edge-AI applications.