Brian P Railing
School of Computer Science
College of Computing
Georgia Institute of Technology

Date: February 13th, 2015 (Friday)
Time: 3:00 PM - 5:00 PM
Location:  KACB 3100

Committee Chair:
Prof. Thomas M. Conte

Committee Members:
Prof. Santosh Pande
Prof. Richard Vuduc
Prof. Sudhakar Yalamanchili

Abstract:

  Computer architecture has looming challenges with finding program parallelism, process technology limits, and the limited power budget.  To navigate these challenges, a deeper understanding of parallel programs is required.  I will discuss the task graph representation and how it enables programmers and compiler optimizations to understand and exploit dynamic aspects of the program. 

  I will present Contech, which is a high performance framework for generating dynamic task graphs from arbitrary parallel programs.  The Contech framework supports a variety of languages and parallelization libraries, and has been tested on both x86 and ARM.  I will demonstrate how this framework encompasses a diversity of program analyses.
  This proposal will present four approaches to classifying and understanding parallel programs.  The approaches classify the parallelism expressed by the program, the communication of the program, and architectural resources required by the program.  Each approach can provide different insights into parallel programs, which can be leveraged by computer architecture, compilers, or programmers.  This proposal will also explore possible future applications of the insights.