The rapid growth of deep neural networks (DNNs) for artificial intelligence has increased the demand for energy-efficient computing. DNN workloads rely on compute- and data-intensive multiply-accumulate (MAC) operations, and in traditional von Neumann architectures, the movement of data between memory and logic dominates their energy and latency. Compute-in-memory (CIM) addresses this bottleneck by performing MAC operations within the memory array. This dissertation focuses on the design and evaluation of CIM and embedded memory arrays based on ferroelectric devices, which offer non-volatility, CMOS compatibility, and low-energy switching. The dissertation first presents a current-mode CIM chip based on ferroelectric field-effect transistors (FeFETs), with integrated readout and a programming scheme to reduce device variation. To tackle the challenges of resistive readout, the dissertation then configures FeFETs as ferroelectric non-volatile capacitors (nvCaps) and presents a charge-domain CIM chip, demonstrating non-destructive capacitive readout with on-chip sensing and evaluating the impact of device characteristics on inference accuracy. Finally, a design space exploration of an embedded non-volatile memory with non-destructive readout explores nvCap applications beyond CIM. Based on a proposed back-end-of-line (BEOL) compatible 3D fin nvCap, this study evaluates whether single-row readout achieves sufficient sense margin under bitline parasitics, its sensitivity to device, circuit, and array parameters, and its energy consumption against other emerging memories. Together, these works show the potential of ferroelectric devices for energy-efficient computing and storage at the edge.