The objective of the proposed research is to develop oxide semiconductor transistors and gate stacks that enable reliable, dense memory and compute integration within the limited thermal budget of monolithic three-dimensional systems. The work addresses the coupled tradeoffs among threshold voltage, drive current, and bias stability through device architecture and gate-stack engineering. Completed studies demonstrate tungsten-doped indium oxide nanosheet transistors with gate-all-around control, improved performance and stability using HfO₂/ZrO₂/HfO₂ (HZH) gate stacks, and four-tier ferroelectric memory operation at 125 °C. Complementary studies examine HZH reliability in silicon FinFETs and ferroelectric transistor arrays for analog in-memory computing. Building on these results, the remaining research will establish practical contacted gate pitch scaling strategies for InOₓ, IWO, and IGO transistors by jointly reducing channel and contact lengths in structures with repeated gates and source/drain contacts. A second direction will combine HZH with SiO₂ interlayer treatments, including radical processing and high-pressure annealing, to develop a reliable low-temperature CMOS gate stack for sequential complementary FET integration. Electrical and reliability measurements will identify scaling limits and process conditions that preserve transistor performance while protecting previously fabricated device tiers. These studies aim to establish experimentally supported design guidelines for vertically integrated memory and future logic technologies.