This dissertation presents high-resolution digital-alike analog-to-digital converter (ADC) architectures and design automation techniques for improving energy efficiency, scalability, and design productivity in advanced CMOS technologies. First, an automated design methodology is developed for first- and second-order VCO-based delta-sigma ADCs. The proposed framework integrates architecture-level exploration, circuit sizing, and simulation-based optimization to reduce the manual effort and design time required for analog and mixed-signal circuits. Second, a third-order continuous-time delta-sigma modulator using a phase-time two-step quantizer is presented. By combining VCO-based and time-domain quantization techniques, the proposed architecture achieves high-resolution conversion with low power consumption. Finally, a high-resolution pipeline-SAR ADC is developed using a driver-relaxed input interface, capacitor mismatch shaping, and a power-efficient closed-loop dynamic residue amplifier. These techniques improve input drivability, robustness, and conversion efficiency without requiring intensive calibration. Together, these works demonstrate how digital-alike circuit techniques, architectural innovation, and design automation can enable scalable and energy-efficient high-resolution ADCs.