This thesis presents an open-source, Python-driven framework designed for the synthesis of mixed-signal reconfigurable integrated circuit architectures, including large-scale Field Programmable Analog Arrays (FPAAs). The methodology begins with a high-level abstracted application specification, which is subsequently organized into islands as algorithms. By augmenting the capabilities of the ASHES software, the framework executes the placement and routing for each individual island before finalizing the routing across the entire system. Furthermore, this tool operates in tandem with ASHES to facilitate the synthesis of reconfigurable analog and mixed- signal layouts using programmable standard cell components. Once manufactured, the resulting hardware can be programmed via the ASHES environment, which incorporate the Versatile Place and Route (VPR) open-source tool.   A foundational element of this synthesis approach relies on crucial recent advancements in programmable standard cells that employ Floating-Gate (FG) devices to achieve high-precision parameter control. These FG-based innovations are pivotal, as they allow for elevated levels of abstraction in analog computation and make large-scale analog synthesis feasible. While this methodology is comprehensively demonstrated through the synthesis and tapeout of configurable chips utilizing a 350nm standard cell library, the underlying techniques are highly adaptable and can be generalized to other technology nodes, such as 130nm, 65nm, and 16nm.