As processor technology scales to advanced nodes, increasing power density and tighter integration constraints expose fundamental limitations in the area overhead and voltage transition speed of conventional off-chip and on-chip voltage regulators. This work presents a comprehensive study of power delivery and management in 3D-stacked systems using back-end-of-line (BEOL) compatible oxide channel transistors, spanning device characterization, circuit design, reliability analysis, and system-level evaluation. 
A reconfigurable M3D SC DC-DC converter for dynamic voltage and frequency scaling (DVFS) in systolic arrays is first proposed, supporting multiple voltage conversion ratios and three discrete voltage scaling modes suitable for neural network inference workloads targeting 3.3V-to-sub-1V conversion. Beyond the 3.3 V input, high-voltage operation is addressed for heterogeneous 3D (H3D) systems, where amorphous tungsten-doped indium oxide (IWO) power transistors with gate-to-drain offset regions and a cascaded hybrid DC-DC converter topology are proposed for 12V-to-0.7V step-down conversion. To characterize the long-term reliability of the converter, a comprehensive bias temperature instability (BTI) analysis framework is developed, integrating AC stress characterization, machine learning (ML)-assisted compact modeling, thermal simulation, and Simulation Program with Integrated Circuit Emphasis (SPICE)-level aging simulation. A system-level evaluation framework is developed that integrates cycle-accurate workload traces from gem5, converter efficiency models, and power delivery network (PDN) parasitics to compare five power delivery configurations across 8-, 16-, and 32-core processor systems. M3D per-core converters achieve substantial energy savings while occupying significantly less planar die area than on-chip solutions, demonstrating that M3D integration of BEOL-compatible DC-DC converters is a viable and scalable approach to power delivery in advanced many-core processors.