The objective of the proposed research is to address the scaling bottlenecks and static power inefficiencies of SRAM by investigating monolithic 3D (M3D) integration of back-end-of-line (BEOL)-compatible amorphous oxide semiconductor (AOS) memories, including capacitive topologies such as eDRAMs and gain cells and AOS-based SRAM, to address conventional SRAM’s scaling and power limitations while preserving its most desirable attributes. Specifically, this work seeks to determine how key AOS device characteristics, including operating voltage, current drive, parasitic capacitance, retention, and variation tolerance, propagate through bitcell and array design to shape the energy, latency, density, and scalability of monolithically integrated 3D memories. To this end, the research develops compact-model and logical-effort-based evaluation frameworks that connect device calibration and SPICE-level circuit analysis to cycle-accurate architectural benchmarking, enabling rigorous study of AOS memories in both conventional memory hierarchies and reconfigurable systems.