Title: Scheduling in Semiconductor Manufacturing

Date: 04/13/2026

Time: 11:30 am – 1:00 pm ET

Location: 

• Online:       https://teams.microsoft.com/meet/24437253000457?p=9iumfJ8WEwfIhkvQNI

                      Meeting ID: 244 372 530 004 57

• In person: Coda Building, 10th Floor, Conference Room Coda C1015 Vinings

                   756 W Peachtree St NW, Atlanta, GA 30308

Committee

• Advisor:Dr. Pascal Van Hentenryck, A. Russell Chandler III Chair — H. Milton Stewart School of Industrial and Systems Engineering, Georgia Institute of Technology
• Dr. Chelsea C White III, Schneider National Chair in Transportation and Logistics — H. Milton Stewart School of Industrial and Systems Engineering, Georgia Institute of Technology
• Dr. Alan Erera, Manhattan Associates/Dabbiere Chair and Associate Chair for Research — H. Milton Stewart School of Industrial and Systems Engineering, Georgia Institute of Technology
• Dr. Leon F McGinnis, Professor Emeritus — H. Milton Stewart School of Industrial and Systems Engineering, Georgia Institute of Technology
• Dr. Reha Uzsoy, Clifton A. Anderson Distinguished Professor — Edward P. Fitts Department of Industrial and Systems Engineering, North Carolina State University

Abstract

Semiconductors are a critical enabling technology, and scheduling in wafer fabrication is a key driver of throughput and supply-chain resilience. Yet the scheduling problems arising in modern fabs are highly complex, involving batching, machine dedications, setup times, multi-chamber tools, and critical queue times (CQTs). In practice, most fabs still rely on dispatching rules that are fast and simple to implement but struggle to enforce some of these technological constraints and remain myopic to high-quality solutions. This thesis addresses this gap through both theoretical research and industrial application, by developing advanced Constraint Programming (CP) models that exploit the structure of semiconductor scheduling problems and by validating them on real wafer-fab data from an industry partner.

The thesis focuses on the batching paradigms that arise in key bottleneck areas of wafer fabs. For parallel batching (p-batching) in the diffusion area, it develops new solver-independent CP models for incompatible job families, and extends them to incorporate family-machine dedications, multiple batch-bound functions, and CQTs. These contributions are complemented by an industrial application chapter, where the resulting models exploit the problem structure to decompose real fab instances and solve schedules with up to 400 jobs (10,000 wafers) in a matter of seconds, producing solutions up to 13% better than actual fab performance. 

For s-batching with minimum batch sizes, motivated by the photolithography and ion implantation areas, the thesis introduces versatile CP models that can solve different variations of s-batching, a capability not shared by existing methods in the literature, which can only solve a specific s-batch variation. The proposed CP models additionally outperform existing mixed-integer programming and meta-heuristic approaches, generating schedules up to 20% better while being up to six times faster. The thesis further extends the initially proposed models and presents a more compact CP model for the ion implantation area in a wafer fab that finds solutions up to 25% better on larger instances with up to 500 jobs (12,500 wafers).

Finally, the thesis integrates the proposed parallel and serial batching ideas into a flexible job shop scheduling framework for wafer fabs that unifies parallel batching tools, multi-chamber machines with setups between wafers, and multi-step CQTs. This theoretical framework is complemented by an industrial application chapter on large-scale instance derived from a real wafer fab, where the resulting model considers more than 600 tasks and individually schedules over 8,600 wafers at a detailed chamber level. The results suggest that within one-hour time limit, the model improves overall throughput by about 13%. Overall, the thesis shows that modern CP, when combined with problem-specific modeling, decomposition, and industrial validation, can substantially narrow the gap between detailed optimization models and the dispatching rules used in practice.