The objective of the proposed research is to develop and validate compute-in-memory (CIM) circuits and systems for accelerating deep neural network inference, with a focus on state-space models (SSMs) where conversion and data movement dominate energy and latency. Multiple design topologies are examined, including fully digital baselines, per-layer-digitized CIM, and end-to-end low-conversion pipeline architectures. Within this framework, a fully analog SSM CIM architecture (FAST-CIM) is implemented, combining analog vector–matrix multiplication with an analog recurrent state update, and validated in silicon. At the architecture level, the impact of conversion rate, precision, buffering, and analog links on energy and delay is quantified. The work also outlines a PWM time-domain CIM path and a system-level evaluation plan for full end-to-end models, enabling scaling to larger models and tasks.