In the field of Semiconductor R&D, the primary goal remains to make compute and memory technologies more compact, faster, energy efficient, and reliable than the existing state of the art. This is even more true in the modern era of Artificial Intelligence where the hardware choice can be a game changer, saving costs by virtue of faster and efficient design, development and deployment. For a long time, this objective was achieved by scaling down Silicon transistors with innovations spanning device structure designs, fabrication techniques, and lithography tools. However, this continuous scaling is a costly endeavor, where the return on investment is diminishing. As an alternative to the traditional Si CMOS based technologies, Emerging Devices and Technologies are explored. Example include non-volatile memories such as ferroelectrics that can store information in a few nm thick films of specialized materials, and architectures such as in-memory compute or in-memory search that break the memory-wall problem. While these candidates are promising, they pose an important question that needs to be answered: Are these Emerging Ferroelectric Devices and Technologies as reliable as the gold-standard Si CMOS Technology? This thesis attempts to answer this very question by performing a comprehensive study, spanning device and array characterization, physical modelling, and circuit simulations, and shines the light on critical reliability challenges that need to be solved.