The objective of the proposed research is to develop machine learning–driven Electronic Design Automation (EDA) methods that enhance design efficiency and scalability across both 2D and 3D integrated circuits. Specifically, this work focuses on developing ML algorithms that improve final design outcomes and productivity in physical design (PD) implementations. The proposed research includes (1) reinforcement learning–based optimization frameworks for 2D/3D ICs, (2) differentiable congestion optimization methods for 3D ICs, and (3) LLM-driven buffer tree generation for physical design. In the next stage, we plan to extend this work toward LLM-enhanced and GPU-accelerated design automation flows, enabling fast and scalable physical design for advanced technology nodes.