The objective of this research is to elucidate the mechanisms governing reliability in ferroelectric field-effect transistors (FEFETs) and to develop strategies for enhancing their endurance through electrical experiments and physics-based simulations. This work investigates the reliability degradation mechanisms in ferroelectric field-effect transistors (FEFETs), with a particular focus on the interplay between the ferroelectric (FE) layer and the interfacial layer (IL). We report a previously unexplored effect, the first switch effect in FEFETs. Our results reveal that the initial polarization event, or the first-switch that occurs when a voltage is applied to the gate of a FEFET, induces significant defect generation within the IL, accounting for nearly half of the total subthreshold slope degradation before memory window closure. Further, correlated measurements of memory window, read delay, and gate leakage identify slow electron traps near the IL as the dominant contributors to long-term degradation. Complementary Ginestra™ simulations confirm that the FEFET degrades in two distinct stages: the first switch degradation and cycling degradation. By coupling experimental characterization with physics-based modeling, this work establishes a mechanistic understanding of IL-driven and FE-driven degradation and outlines pathways for device optimization to achieve high-endurance, reliable FEFETs for non-volatile and compute-in-memory applications.