Abstract

Artificial intelligence (AI) is now pervasive – augmenting our capabilities and enriching our experiences – but it was less than a decade ago that the first key breakthroughs in deep learning were made. Tremendous progress has since been made in expanding AI applications as well as the accuracy of AI models, often by generating massive models that are trained on large datasets. However, this explosive growth in model size and the concomitant increase in required compute is unsustainable without significant semiconductor innovations across the hardware stack from materials and devices at the transistor level up through packaging. In this talk, advances needed to sustain continued CMOS scaling will be discussed with a focus on materials and architectural progress in devices that harness the third dimension. In looking beyond transistor performance, a non-von Neumann computational approach will be described that envisions artificial neural networks mapped to arrays of non-volatile memory (NVM) elements. These NVM elements act as artificial synapses and encode the weights of a neural network that execute analog compute operations in-memory, thereby enabling significant power performance benefits. It will also be shown that co-optimization of materials, algorithms and architecture is needed to unlock the promise of analog in-memory compute. Lastly, enhanced connectivity and scalability using a chiplet approach will be described to allow for seamless integration of disparate compute components. Indeed, novel semiconductor technologies and architectures combined with advanced packaging techniques that address key bandwidth challenges will drive the AI of tomorrow. 

Bio 

Dr. Narayanan received his B.Tech. in Metallurgical Engineering  from the Indian Institute of Technology, Madras (1995), and his M.S. (1996) and Ph.D. (1999) in Materials Science and Engineering from Carnegie Mellon University. After completing post-doctoral research at Arizona State University, Dr. Narayanan joined the IBM T. J. Watson Research Center in 2001 where he pioneered High-ĸ /Metal Gate Research and Development from the early stages of materials discovery to development and implementation in manufacturing. These High-ĸ /Metal Gate materials form the basis of all recent IBM systems processors and of most low-power chips for mobile devices. Currently, Dr. Narayanan is an IBM Fellow where he leads a worldwide IBM team developing Analog Accelerators for AI applications and Semiconductor Pathfinding for advanced CMOS Logic & Chiplets. Dr. Narayanan is an IEEE Senior Member and was elected a Fellow of the American Physical Society in 2011. He was awarded the Distinguished Alumni Award from Indian Institute of Technology, Madras for the year 2025. He is an author of over 100 journal and conference papers, holds more than 230 US patents, and has edited one book: “Thin Films On Silicon: Electronic And Photonic Applications”