The objective of the proposed research is to enable the use of emerging machine intelligence techniques for high-level digital hardware design, while supplementing these approaches with robust datasets and benchmarks to support intelligent design frameworks. The increasing use of hardware accelerators for domain-specific applications in science and machine learning has driven demand for platforms like field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). Tools such as high-level synthesis (HLS) enable developers to target these platforms using high-level languages like C++, rather than traditional hardware description languages (HDLs) like Verilog, raising the level of design abstraction. With the rise of deep learning and generative AI, researchers are also increasingly interested in incorporating machine intelligence into hardware design workflows. This includes fast, automated performance optimization of HLS designs using predictive machine learning models and the use of large language models (LLMs) to generate HLS design source code from natural language descriptions. However, these machine intelligence approaches depend on robust datasets, benchmarks, and evaluation methods, which are still limited in the HLS domain. Additionally, challenges remain in generalizing deep learning methods to traditional FPGA and ASIC implementation flows and in leveraging HLS benchmarks and designs to support comprehensive benchmarking of downstream implementation flows. To address these challenges, this research aims to develop new HLS dataset frameworks, innovative HLS benchmarking approaches, and end-to-end LLM automation frameworks for HLS design and optimization utilizing tool-guided feedback and ML performance prediction. By tackling key challenges in generalization and robustness, we hope to empower the academic community to confidently innovate electronic design automation (EDA) workflows.