Sai Saravanan Ambi Venkataramanan
Co-advisors: Prof. Mark D Losego, Dr. Mohan Kathaperumal

will propose a doctoral thesis entitled,

Packaging and design of inductors embedded in thin glass interposers for > 5 V – 1 V Integrated Voltage Regulators

On

Friday, June 6 at 9:30 a.m.
Pettit 102B conference room
and/or
Virtually via MS Teams
https://teams.microsoft.com/l/meetup-join/19%3ameeting_MTNiMzMzYTItNmRh…

Committee
           Prof. Mark D Losego – School of Materials Science and Engineering (co-advisor)
           Dr. Mohan Kathaperumal – School of Electrical and Computer Engineering (co-advisor)
           Prof. Anju Toor – School of Materials Science and Engineering
           Dr. Himani Sharma –  School of Materials Science and Engineering

Abstract
Generative artificial intelligence (AI) models require billions of feature parameters for training and execution. At peak performance times, the transistors or system-on-chips (SoCs) require continuous power of 700-1400 W. CMOS compatible chiplets and most advanced Integrated Circuits (ICs) operate at < 1 V, hence the current requirements translate to thousands of amperes [1]. To bring high power supply to the System-on-Chips (SoCs) while maintaining system efficiency, signal power is conventionally brought in at high voltages to minimize line current. Integrated Voltage Regulators (IVRs) are Point-of-Load (PoL) DC-DC convertors that help to step down high voltage, low current input to high current low voltage output desirable for ICs. It is imperative that IVRs are located as close as possible to the SoC to avoid routing losses in between IVR and SoC. Miniaturized IVRs that are embedded in thin semiconductor interposers empower vertical power delivery directly underneath SoCs for near ideal PoL regulation. In the context of IVRs, inductors are passives that supply electrical energy to the load when field effect transistors (FETs) are in the OFF cycle. The focus of this research is studying inductors for vertical power delivery in a buck-based IVR. This problem statement can be decoupled in terms of understanding the loss in efficiency due to a) the core material, b) winding or footprint design, and c) package fabrication and associated reliability constraints. The core must have a) have high permeability to enable miniaturization, b) withstand high currents (saturation bias), and c) low switching losses (eddy and hysteresis). Thus, tight requirements of an ideal inductor were proposed earlier for 12 V – 1 V conversion: relative permeability (µr) of 65, loss tangent (tanδ) < 0.012, and saturation magnetization (Hsat) of > 6 kA/m, operation frequency range of > 1 MHz [2]. Previous work has shown that high permeability materials typically have lower saturation, while low permeability materials can perform at higher peak currents. This was attributed to metallic filler shape but not analyzed in detail [2,3]. The winding design should have low DC and AC resistance, while be able to leverage the thickness and spacing between the copper coils (number of turns) to match the desired inductance and current rating for a given footprint. In addition, the fabrication process for embedding in thin glass interposers must consider known package failures such as a) glass cracking due to thermal stress on copper expansion [4], b) magnetic material leaching into copper [5], and c) warpage due to coefficient of thermal expansion (CTE) mismatch.

To analyze this overarching goal from various perspectives, this study will be devoted to:

1.    fabrication and > 1 MHz characterization of soft magnetic composites for power delivery
2.    simulation of eddy and hysteresis loss models using Ansys Maxwell to validate the results with experiments to predict the trend at higher frequencies
3.    demonstrate embedding of inductors in glass interposers using semi-additive processing and study the reliability of the fabricated packages.
References:
[1] https://www.vicorpower.com/resource-library/articles/high-performance-c…
[2] C. A. Alvarez, “Design and demonstration of embedded inductors for high-voltage integrated voltage regulators,” Ph.D. dissertation, Georgia Institute of Technology, 2021.
[3] P.Murali, “Materials and processes for high conversion ratio high efficiency package embedded inductors for Integrated Voltage Regulators,” Ph.D. dissertation, Georgia Institute of Technology, 2023.
[4] H. Wang et al., “Failure Mechanisms Investigation of Through Glass via (TGV) Under Thermal Annealing and Shock,” 2024 25th International Conference on Electronic Packaging Technology (ICEPT). IEEE, pp. 1–6, Aug. 07, 2024. doi: 10.1109/icept63120.2024.10668558.
[5] K. Bharath et al., “Integrated Voltage Regulator Efficiency Improvement using Coaxial Magnetic Composite Core Inductors,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). IEEE, pp. 1286–1292, Jun. 2021. doi: 10.1109/ectc32696.2021.00208.