Title: Efficient Inter-Process Communication Mechanisms for Data-Centric Computing
Date: May 22, 2025
Time: 11:30 AM – 1:00 PM ET
Location: KACB 3100 and Zoom (https://gatech.zoom.us/j/2198386303)

Misun Park
Computer Science PhD Student
School of Computer Science
Georgia Institute of Technology
Committee:
Prof. Ada Gavrilovska (Advisor) - School of Computer Science, Georgia Institute of Technology
Prof. Hyesoon Kim (Advisor) - School of Computer Science, Georgia Institute of Technology
Prof. Alexandros Daglis (Advisor) - School of Computer Science, Georgia Institute of Technology

Abstract:
Modern data-intensive applications, such as large-scale analytics pipelines, graph processing workloads, and multimodal AI inference systems, are increasingly constrained by the overhead of transferring and managing large volumes of intermediate data across complex memory hierarchies. This thesis explores how inter-process communication (IPC) services, central to data movement in these application workflows, can be redesigned to overcome the limitations of existing solutions. Specifically, we leverage architecture- and system-level advances, such as memory accelerators and fine-grained control interfaces, to create a new class of IPC mechanisms that achieve improved efficiency and performance by adapting IPC executions to data volume, access patterns, and dynamic runtime conditions.
First, the thesis introduces Pocket, a redesigned IPC system that integrates lightweight resource management directly into the messaging interface. Rather than treating IPC as a passive channel, Pocket allows messages to carry hints about resource expectations, effectively enabling just-in-time resource (re-)allocation and receiver-side adaptation. By integrating resource awareness into IPC semantics, Pocket reduces memory pressure and enables dynamic resource amplification without requiring centralized scheduling. Second, the thesis presents Rocket, an IPC runtime that offloads memory copy operations to Intel’s Data Streaming Accelerator (DSA). Rocket does more than simply shift work to hardware—it provides insights into when offloading is beneficial, and when it may backfire due to cache interference, polling overhead, or synchronization delays. Based on this analysis, Rocket introduces a suite of optimized IPC stacks which integrate new execution modes, hybrid polling mechanisms, and cache-aware transfer options. The design of Rocket provides offload controls which result in efficient overlap of computation and data movement, particularly in high-volume, multi-stage application pipelines. Finally, the thesis examines how these IPC optimizations are brought together in practice within real-world, data-heavy workloads such as multimodal AI inference, analytics pipelines, and video processing tasks. This part of the thesis work characterizes application behavior and system load, and develops lightweight runtime decisions based on simple workload signatures or mode selection heuristics, to narrow the gap between general-purpose IPC stacks and finely tuned, task-specific solutions.
Together, Pocket, Rocket, and its adaptive extension demonstrate a practical and scalable path toward IPC systems that match the needs of modern applications. By aligning IPC logic with hardware capabilities and application-level variation, this thesis presents a new design space for performance-aware IPC in the era of hardware-accelerated, data-centric computing.