This dissertation explores optimization-driven techniques to enhance the performance of digital integrated circuits. The work comprises two main efforts: first, the design and implementation of baseband processors for optimal mm-Wave beamforming; and second, the estimation of worst-case supply-voltage (Vdd) droops in Power Delivery Systems (PDSs) at design time using numerical optimization. Modern mm-Wave beamformers are typically implemented in the analog domain due to the high power demands of fully digital solutions. However, their performance degrades significantly in dynamic scenarios with moving transmitters. This dissertation presents two digital baseband processor architectures—and corresponding test chips—tailored for such conditions. The first test-chip is the earliest known implementation of adaptive optimal mm-Wave beamforming that maximizes signal-to-interference-plus-noise ratio (SINR) in the presence of multiple moving interferers, assuming a stationary signal of interest. The second processor builds on the first architecture to support signal tracking, enabling SINR-optimal beamforming even when the transmitter of interest is also in motion. Reliable estimation of worst-case Vdd droop is essential for optimizing power delivery and overall SoC efficiency. Yet, existing design methodologies overlook key system-level interactions—such as those across voltage domains, and those involving the board, socket, and package—as well as architectural constraints on load current profiles. To address these challenges, this dissertation introduces DroopSolver, a SPICE-accurate framework based on numerical optimization that estimates worst-case droop in multi-domain SoC power delivery systems.