Tensor-algebra applications are made up of operations that are independently analyzed and optimized when mapping them onto custom accelerators. While this approach works well for GEMMs with good reuse, we show that several tensor-algebra applications have operations with skewed aspect ratios which severely limits the reuse, making them memory bound. Therefore, the approach of optimizing an individual kernel or tensor operation is severely limiting. This work presents architectures and mapping strategies for efficient execution that improve the speedup on tensor-algebra applications where individual operations have low or mixed reuse. We first propose a taxonomy to classify dataflows for pipelining between two operations, and a cost-model OMEGA. We then propose PipeOrgan, which extends this to a larger pipeline depth and proposes a new class of spatial organization strategies for parallel pipeline dataflows, which minimize on-chip communication from producer to consumer. However, generalizing inter-operation reuse on tensor-algebra applications also requires considering applications like CG with complex DAGs, and delayed downstream dependencies where traditional inter-operation pipelining does apply. We propose SCORE, a scheduling strategy that classifies dependencies in the DAG and proposes data flow and tiling strategies at the register file level for applications like Conjugate Gradient. However, the design-space of buffer allocation strategies at the level of on-chip scratchpad explodes, especially for CG, which puts a burden on the scratchpads that need to allocate the lines in the buffer explicitly. Caches, on the other hand, have policies with a myopic line-level view. Therefore, we propose CELLO, an accelerator that uses SCORE to determine the data flow, and CHORD, a proposed hybrid implicit/explicit buffer mechanism for buffer allocation reducing the burden on the compiler. Finally, we propose HARP, a taxonomy to classify emerging hierarchical and heterogeneous architectures for mixed-reuse workloads such as LLMs with high- and low-reuse operations in the same application cascade.