Analog-to-Digital Converters (ADCs) are essential components in modern electronics, enabling the conversion of physical signals into digital form. While most research focuses on improving ADC performance, other elements in the signal chain often become system bottlenecks. This thesis introduces a novel concept: signal-chain optimized ADC design, which co-designs both ADCs and other signal chain components to enhance overall system performance. Initially, I designed and taped out an input-driving-buffer-embedded NS SAR ADC, which successfully reduces input driving requirements while achieving state-of-the-art performance. Additionally, the Amplifier-Reused-In-Loop Buffering (AILB) technique is proposed and validated in silicon, which further reduces noise limitations. Finally, a light-to-digital converter (LDC) is developed to extend the idea to current sensing applications, reducing the power consumption of the system. This research will benefit edge devices, such as wearables and IoT applications, enabling high-precision tasks with extended battery life.