This dissertation explores the integration of ferroelectric field-effect transistors (FEFETs) into logic-embedded and 3D NAND flash memory platforms, addressing key challenges such as low write voltage and large memory window (MW) requirements. For logic applications, gate stack engineering, including scavenging techniques and the use of a Ge substrate, successfully reduced the write voltage (Vc) to below 1.5 V, making the FEFET compatible with logic circuits. For 3D NAND applications, a novel approach incorporating an Al₂O₃ layer into the ferroelectric stack achieved a MW greater than 7.5 V, exceeding the 6.5 V threshold required for triple-level cell (TLC) standards. These findings were validated through the fabrication of FEFETs and MOS capacitors. The results demonstrate that optimized gate stack engineering can enable FEFETs for both logic and memory applications, with potential for future improvements leading to broader commercial adoption.