This work presents a comprehensive end-to-end evaluation platform for CMOS and beyond-CMOS technologies. This work encompasses various levels of abstraction while considering various device, interconnect, and memory options across multiple technologies. In the case of memories, the focus has been on spintronic memories including spin orbit torque (SOT), spin transfer torque (STT), and magnetoelectric (ME) based magnetic random access memories (MRAMs). For SOT devices, a comprehensive modeling for spin current generation in nanoscale devices is presented while accounting for the impact of non-uniformity in the electric current density and material properties. For SOT and STT devices rare-event enhancement based methodology has been adopted to evaluate various trade-offs among write error rate (WER), delay, and current. Area saving schemes for SOT-MRAM, with multiple magnetic tunnel junctions (MTJs) on a SOT track using voltage-controlled magnetic anisotropy (VCMA) and STT, are presented while accounting for the detailed trade-offs among voltage drop, WER, energy, and bit density. A study on the impact of scaling technology node from the 14nm node to the 7nm node is presented for MRAM arrays while also evaluating the impact of various back-end-of-line (BEOL) technology options. In addition, at the 7nm node full SOT-MRAM memory system design is presented based on open-source ASAP7 process design kit (PDK). To explore the applications SOT/ME devices for hardware accelerators, novel content addressable memory (CAM) designs are proposed and evaluated. At the 3nm technology node, a PDK has been developed to evaluate various device, interconnect, and technology options. Using gate-all-around field effect transistor (GAAFET) based standard cell library, various BEOL options involving copper and ruthenium are studied using place and route results for benchmark circuits.