The objective of the proposed research is to help close the developer experience gap between software engineering and hardware design, thereby empowering more people to design specialized hardware and advancing towards an agile workflow for hardware design. Traditional hardware design flows require designers to write explicitly parallel, low-level register-transfer level (RTL) code in a hardware description language (HDL) such as Verilog or VHDL. Modern high-level design tools, such as high-level synthesis (HLS), promise to raise the level of abstraction by synthesizing high-level languages like C++ into Verilog and VHDL, but they still require significant hardware design expertise and specialized techniques to create performant, resource-efficient hardware designs. This research aims to facilitate high-level hardware development workflows through works on “acceleration”—providing exemplars of efficient HLS accelerators of modern machine learning (ML) models—and on “accelerating acceleration”—developing tools that improve high-level workflows in general.