Present-day hardware with limited on-chip memory capacity falls short of meeting the speed and energy-efficiency requirement for data-intensive applications such as Artificial Intelligence, Internet of Things etc. This is due to the need for extensive data transfer between processor and off-chip memory. To circumvent the “memory-bottleneck” issue present in von-Neuman architecture-based systems, alternative compute systems such as near memory computing (NMC) and in-memory computing (IMC) have been shown to be promising. NMC aims at reducing energy consumption and latency from data transfer by bringing the memory closer to the processor. Monolithic 3D integration (also referred to as M3D) of stacked logic and memory is a potential way to realize NMC as the physical distance between logic and memory can be brought down to micrometer range. IMC, on the other hand, obviates the data movement by merging memory and computation into single devices. However, the success of realizing NMC and IMC largely depends on the availability of high performance back-end-of-line (BEOL) transistors and non-volatile memory technologies with novel characteristics, respectively. The objective of this PhD dissertation is to develop ultra-high density cache memory and ferroelectric FET (FEFET)-based computational memory for enabling near-memory and in-memory computing which can mitigate the energy-inefficiency and latency. M3D gain-cell memory, which is a potential enabler of NMC due to high memory density and vertical stacking on top of logic, requires BEOL FET with high-performance and high threshold voltage (VT) stability. On that front, a BEOL dual-gate (DG) FET is demonstrated to synergistically improve the device performance and VT stability and a comprehensive reliability model is developed to elucidate the VT shift mechanisms. This thesis also demonstrates a novel idea of engineering ferroelectric gate stack using superlattice (SL) structure which enhances multi-state memory programmability in FEFET and thus can enable denser memory and novel functionality such as analog weight cell to accelerate in-situ training and inference of deep neural networks (DNN). Furthermore, this thesis focuses on developing scaled Si-channel FE-FinFET and explores its potential application for accelerating edge inference in DNN.