In the roughly thirty years since the development of Shor's Algorithm, academic and industry researchers have sought the elusive fault-tolerant quantum computing platform capable of computational problems with a provable advantage over classical computing systems. This has led to the development of many different physical methods for creating quantum bits, or qubits, including ion-trap devices, superconducting Josephson-junction-based qubits, neutral atom arrays, measurement-based qubit designs, and semiconductor spin qubits. While each of these platforms offer their own unique advantages and disadvantages, quantum computing technology has not yet achieved the scale required for fault-tolerant computation of practically useful algorithms. This thesis demonstrates a multi-disciplinary path towards useful quantum computation: the development of advanced quantum-classical co-design through low latency feedback and on-board computation for improved characterization and calibration of quantum systems. The work begins with a demonstration of both the promises and limitations of noisy intermediate-scale quantum (NISQ) computers through the implementation of a Quantum Hopfield Associative Memory (QHAM) on superconducting qubit platforms. Observing the stark difference between simulated and hardware-executed results of this system, including a noise model which provided a poor prediction of hardware performance, the work moves towards the development of improved characterization and calibration using FPGA-based methods. First, an FPGA-based accelerator demonstrates exponential speedup of quantum state tomography which can be used to better understand quantum state preparation and is extendable to more complex characterization algorithms like process and gate set tomography. Then, low latency feedback is used to demonstrate single- and few-shot calibration protocols for quantum gates, providing significant improvement in the accuracy of quantum computing systems given sufficiently low-latency feedback in on-board control hardware such as FPGAs or CMOS ASICs. With these works, this thesis demonstrates the advantage available through quantum-classical hardware co-design using low-latency on-board digital compute and feedback, which as of this thesis has had only limited demonstrations in literature.