The objective of the proposed research is to explore the engineering of gate stacks for the application of ferroelectric (FE) layers to two distinct platforms. Addressing the need for a low writing voltage in logic applications, this study adopts scavenging techniques and utilizes Ge semiconductor. Furthermore, to achieve a large memory window (MW) for NAND applications, the insertion of an Al2O3 layer is employed, with validation conducted in ferroelectric field-effect transistors (FEFETs). Future endeavors aim to enhance the characteristics of the ferroelectric layer by evaluating and comparing FE layers deposited using thermal atomic layer deposition (ALD) or plasma ALD with FEFETs. Additionally, by fabricating FEFETs on silicon-on-insulator (SOI) wafer substrates and evaluating them, the study intends to investigate whether the scavenging technique, proven effective in interlayer (IL) engineering, can improve characteristics such as leakage in FEFETs using SOI wafers and the scavenging technique.