The objective of the proposed research is to develop a Configurable and Programmable Processing-in-DRAM (CR-PIM) architecture tailored for high-throughput streaming data applications. Specifically, our goal is to design an application that comprises arrays of logic cores, which can be either homogeneous or heterogeneous. These logic cores will be connected to distributed memory using an on-chip network that supports both static and dynamic reconfigurations, enabling efficient streaming data processing. Our existing work (DRBE) has successfully demonstrated the implementation on FPGA platforms for emulating RF signal interactions. Building upon the DRBE concept, our proposal seeks to enhance and modify the idea/architecture incorporating MAC engines and lookup tables to facilitate various types of linear and non-linear data processing. Additionally, we will implement a new configurable Network-on-Chip (NoC) responsible for transferring data between source and destination modules through multiple links, with routing decisions managed by switches. The primary objective is to achieve a design that not only functions correctly but also operate efficiently in terms of power consumption during runtime.