The objective of this research is to provide EDA solutions to address both power and performance in emerging 2.5D and 3D ICs. Due to transistor scaling challenges and power limitations in complex Gigabit Systems on Chip (SoC), chiplet integration is a promising approach to address these issues with the following benefits. First, the chiplet reduces the design complexity, resulting in a lower cost in manufacturing. Moreover, the advancement in 2.5D/3D packaging technology allows high-density connection between chiplets, reducing the bottleneck and improving the full-chip performance. However, the existing EDA design flow failed to provide high-performance commercial-quality 3D ICs. The proposed research aims to resolve the issue, which includes 1) a novel physical design solution to provide commercial quality 3D ICs by mitigating the problems in the placement stage. 2) The EDA design flow to support heterogeneous integration in 3D ICs. 3) The multibit clock clustering technique by applying machine learning to optimize both power and performance in 3D ICs. 4) The design trade-offs between 2.5D/3D integration types to support very large-scale systems for industry-standard applications. 5) Back-side Clock routing design methodology in advance node technology.