This thesis proposed three different ways to improve the energy efficiency of SoCs while meeting Power Delivery Network (PDN) constraints and minimizing Bill of Materials (BoM). The first work quantifies the prohibitive energy-efficiency impact of these margins and proposes two techniques to address them: Dynamic Droop Allocation (DDA) through concurrent domain-Vdd control, and adaptive clocking using the UniCaP architecture. We demonstrate the effectiveness of both techniques on an integrated 4-domain SIMO SoC in 65nm CMOS. Measurements indicate that compared to conventional SIMO implementations, Vdd guardband reductions obtained by UniCaP and DDA are 98% and 40%, respectively. The second work presents an architecture that efficiently reverses power flow in a buck converter at the onset of Sleep to recycle the stored energy stored in the decap before Sleep, thus minimizing transient Sleep leakage losses (Eloss). A fully-digital run-time Eloss optimizer is presented to achieve optimal recycling, and demonstrated in a voltage domain consisting of a duty-cycled, buck-regulated ARM M0 processor. Measurements indicate that 59.4% Eloss reduction is achieved with 3.2-ms Sleep duration. These savings translate to total system energy savings of 56.6% for a duty-cycled processor executing 5K cycles during Active operation. Built upon the first two work, the third work presents a multi-Vdd MEP tracking for duty-cycled systems, monitoring the input energy of the voltage regulator every sleep-run cycle and guides the multi-Vdd toward the optimal point. Measurement results indicate that The resultant EIN provided by the proposed tracker is within 2.2% of the true minimum EIN on average. When compared to the baseline, the proposed work, with and without Recycle operation, offers energy reductions of 1.43x and 1.2x, respectively.