The proposed research's objective is to first reduce the complexity and power overhead of the recent noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC) design. Another major objective is to surpass the limitation of the relatively low speed of the NS-SAR ADCs owing to their extra steps of residue processing. Therefore, a novel ADC architecture with the NS-SAR mechanism is proposed in this proposal. First, the pipeline ADC architecture merging with a two-channel time-interleaving beck-end NS-SAR ADC is employed. Such arrangements address the speed obstacles of the NS-SAR and inherently mitigate the complexity of the loop filter design. Second, using a sub-ranging capacitive digital-to-analog converter as the digital result holder, the proposed pipeline scheme's interstage gain is reused as a driver for the back-end sampling. This technique has the potential to largely mitigate the sampling kT/C noise of the front-end stage ADC, which is beneficial to the ADC power, noise, and resolution concern.