The end of Dennard scaling followed by the slowing of Moore’s law has made computer systems increasingly complex, with the integration of not just multiple types of processing units but also multiple disintegrated chiplets on a single package. The adoption of multi-chiplet architectures by commercial vendors has propelled the need to develop new designs, tools, and methodologies for building high-performance and energy-efficient next-generation systems. Chiplet-based systems introduce several new design constraints and pose challenging research questions. Unfortunately, current state-of-the-art architectures and design methodologies do not efficiently adapt to the new constraints posed by these packaging technologies. Additionally, with the dramatic increase in the usage of Graphics Processing Units (GPUs) for general-purpose computation, it has become particularly important to optimize solutions for them. Thus, there is a broad need to revisit the system research and design approaches for these multi-chiplet GPUs. This thesis addresses some of these challenges by exploring GPU and interconnection system architectures, developing tools and methodologies, and proposing novel designs to enable efficient and tighter integration on next-generation GPU systems. The thesis approaches these objectives in three major directions. First, the thesis delivers tools to enable high-fidelity simulation tools and infrastructure for accurate and efficient exploration of multi-chiplet architectures. Second, it explores design that can enable efficient integration of interposer-based designs by enabling robust design semantics in the interconnection system. Third, it enables workload-aware dynamic power efficiency mechanisms in multi-chiplet GPUs by leveraging the improvement in power delivery systems. Overall, the insights and guidelines provided in this dissertation could serve as a valuable resource for future research and development in the field of chiplet-based GPU systems.