Prahalad Murali

(Advisor: Prof. Madhavan Swaminathan & Co-advisor: Prof. Mark D. Losego)

will defend his doctoral thesis entitled,

Materials and processes for high conversion ratio high efficiency package embedded inductors for Integrated Voltage Regulators

On

Tuesday, November 28 at 1:00 pm

Pettit Microelectronics Building – Room 102 A

And

Via Zoom

https://gatech.zoom.us/j/97718265765?pwd=T3BJN2M5UTVPT2NMUEs0WmJWZTE5UT09

Meeting ID: 977 1826 5765

Passcode: 633456

Abstract

Datacenter advancements demand faster and denser chiplets within a single package, driven by the imperative to meet future performance metrics. The pursuit of faster computing has consequently pushed power delivery boundaries to these chiplets. Traditionally, input voltages in data center racks were uniformly converted to 1 V on the PCB, with modifications to design mitigating IR drop caused by path resistances, thereby maintaining overall system efficiency. However, the limitations of this approach have become apparent due to the emergence of larger packages and higher power density requirements facilitated by increasing transistor density and 3D stacking of chiplets.

To overcome these challenges, there is a paradigm shift towards bringing power at higher voltages to reduce current, and subsequently, copper losses, which are directly proportional to the square of current (I²). Enabling high input voltages into the package substrate necessitates the integration of a single stage of power conversion into the package. Voltage-down conversion involves incorporating actives like Integrated Voltage Regulator (IVR) chiplets and passives like capacitors and inductors to form a buck converter circuit—an efficient topology for high conversion ratio voltage conversions—integrated into the package.

Gallium Nitride (GaN) IVR chiplets are advocated for voltages greater than 5 V due to their wide bandgap compared to Silicon-based Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The use of GaN FETs mandates inductors capable of handling high currents, current ripples, low losses, and generating high inductance to meet the stringent 12 V - 1 V DC-DC down conversion requirements. Achieving inductor efficiency above 95% and system efficiency exceeding 90% is crucial for this purpose. To meet these efficiency targets, exploration of new inductor designs and materials for the magnetic core is essential. To enhance system efficiency and address IR drop challenges, the inductor should be positioned as close to the chiplet as possible.

Current state-of-the-art inductors, integrated into the package core, utilize magnetic pastes for the magnetic core, ensuring compatibility with substrate processing. These inductors generate 2.5 nH of inductance in each of the six phases, capable of handling 8 A current with less than 12 mΩ of total path resistance from the board to the chiplet through the inductor. However, their optimal usage is within the 100-140 MHz range for 1.75 V to 1.08 V DC-DC conversion.

The objectives of this research are to address gaps in understanding the impact of metal filler shape and heat treatment on inductor properties. It includes the fabrication of toroidal and spiral inductors, reliability assessment, and the integration of inductors as close to the chiplet as possible. The research aims to develop models, materials, and processes to investigate the structure-property correlation of metal fillers in a metal-polymer composite for high conversion ratio applications, demonstrate and compare toroidal and stacked spiral inductor designs, and showcase a Redistribution Layer (RDL) embedded inductor spanning multiple buildup layers.

Committee

• Prof. Madhavan Swaminathan – School of Electrical and Computer Engineering and School of Materials Science and Engineering (Advisor)
• Prof. Mark D. Losego – School of Materials Science and Engineering (Co-Advisor)
• Dr. Mohanalingam Kathaperumal - School of Electrical and Computer Engineering
• Prof. Maryam Saeedifard - School of Electrical and Computer Engineering
• Dr. Himani Sharma - School of Materials Science and Engineering