The objective of this research is to explore 3D IC physical design methodologies and develop EDA solutions to evaluate and mitigate power delivery and thermal challenges in high-performance 3D ICs with emerging interconnects and advanced CMOS technology. Specifically, we implement tool flows to enable 3D IC physical design with various design and technology assumptions based on existing EDA software and customized algorithms. Using a novel 3D RTL-to-GDS design flow, we improve the performance of heterogeneous 3D ICs, investigate emerging computing systems such as logic-on-memory stacked 3D CPU, and explore the PPA, power delivery and thermal impacts of 3D integration.     
With a comprehensive analysis of 3D IC power delivery and thermal integrity, we propose EDA methods to quickly analyze thermal sustainability, explore design trade-offs, and generate floorplan and cooling solutions for large-scale 3D computing systems. In addition, we study the trend of power delivery issues in 3D ICs with technology scaling. We identify key power delivery challenges and bottlenecks considering various technology nodes and applications, propose robust 2D/3D PDN structures and design strategies, and evaluate the system-level impacts on PPA and power integrity.