The objective of this research is to investigate power delivery network (PDN) and thermal management constraints in 3-D heterogeneous integration (HI) architectures for compute-in-memory (CIM) applications. First, we investigate design trade-offs in the power delivery network (PDN) of bridge-chip based 2.5-D heterogeneous platforms. We demonstrate that including a PDN in the bridge-chip can provide significant reduction in DC-IR drop, Ldi/dt noise, and high-frequency ripple compared to the baseline. Second, a comprehensive design-space exploration of PDN design for 3-D-HI CIM hardware. A methodology is proposed to evaluate and quantify trade-offs between power delivery design parameters and CIM performance metrics. Next, a device-integration methodology is proposed to quantify the thermal-driven impact of integration architectures on RRAM reliability for CIM applications. Subsequently, we present the thermal evaluation of a back-end-of-line (BEOL)-embedded chiplet integration scheme (polylithic 3-D), where custom chiplets are embedded into the BEOL of a primary tier. Finally, we present a study to evaluate the power delivery constraints for polylithic 3-D integration of BEOL-embedded chiplets. The potential impact of this research and potential future directions are summarized.