The packaging innovations are driven by applications such as fifth-generation (5G) wireless technology. For the radio frequency (RF)/mm-wave systems in the 5G, it is critical to manage the loss and the impedance at the package level to achieve a superior system’s electrical performance. Given the high loss and significant impedance mismatching of current wire/ribbon-bonding technology, a low-loss and impedance-matched fused-silica stitch-chip technology is proposed and studied for polylithic integration of RF/mm-wave systems in this dissertation. A summary of the work is as follows: (1) RF characterization and parasitics extraction are performed for interconnect components on the fused-silica stitch-chip, including coplanar waveguide (CPW) and compressible microinterconnect (CMI). (2) The impedance design of the assembled fused-silica stitch-chip is then investigated and experimentally validated. (3) Furthermore, such integration technology is demonstrated with commercial off-the-shelf (COTS) RF/mm-wave dice (e.g., low noise amplifier) as a scalable chiplet-based module. (4) In addition, alternative off-chip I/O technologies for the fused-silica stitch-chip (e.g., microbump and hybrid-bond) are studied and benchmarked in terms of parasitics for beyond-5G applications.