The objective of the proposed research is to investigate design optimization methods for power delivery networks (PDNs) in packaging. The increasing demand for high operating frequencies and transistor density in integrated circuits (ICs) within high-performance computing systems has led to faster transients and higher currents, causing significant power supply noise and voltage droop. As supply voltage operating margins for ICs decrease due to continued transistor scaling, managing power supply noise below a threshold level has become challenging. We first present a methodology to predict voltage droop caused by current sources in ICs, deriving analytical relations and analyzing the error in predicted values. The effect of current step rise time on voltage droop is also considered, along with error analysis, capturing error bounds for the derived equations. We then introduce two novel approaches for optimizing PDN response using the minimum number of capacitors. First, we propose a knowledge-based method for determining decap design in PDNs, which converges to the minimum decoupling capacitor solution with fewer simulations than full search or random exploration methods (machine learning etc.). Second, we propose an advantage actor-critic (A2C) reinforcement learning (RL)–based method for decap design optimization. This method offers a larger number of optimized decap design solutions, enables multi-port optimization, and allows knowledge transfer to different PDN environments using transfer learning techniques. Furthermore, we focus on optimizing power planes that provide low impedance paths, ensuring power supply noise remains below threshold levels. Using RL-based techniques, we obtain optimized shapes and areas for multiple power plane designs that satisfy design requirements. This technique has been applied to multi-layer PDNs for high-speed signaling.