Radio Frequency (RF) applications like RF Machine learning and real-time RF environments (radar, electronic warfare) have constraints of high accuracy in data formats, high throughput and low latency. Processing-in-Memory (PIM) accelerators have shown promise for computation in traditional Machine learning applications involving dot product of matrices but are restricted in data format and precision. Field Programmable Gate Array (FPGA) based systems have been designed to process RF computations in real-time systems, but they cannot simultaneously handle the high throughput (>100MHz) in wide bandwidth RF systems and low latency (of the order of micro-seconds) of real-time operation.
First, this thesis focuses on extending the capability of In/Near Memory hardware accelerators to handle RF data with high precision. A fully digital processing-in-memory accelerator for Vector Matrix Multiplication with support for flexible precision, floating point and complex numbers is designed. The test-chip is fabricated in 65nm CMOS and demonstrates a measured compute efficiency, normalized to memory size, of 34 GOPS/W/KB. The PIM accelerator can enable in-memory radio frequency machine learning and signal processing computation. Second, the thesis proposes an ASIC based near-memory distributed control architecture targeting computation with deterministic buffering and distribution of real-time streaming digital RF data with high throughput, specifically for sparse calculations. A small-scale prototype design for the distributed control is fabricated in 28 nm CMOS on a 6sq.mm. die for application to a real-time RF emulator testbed with requirements of high throughput and deterministic, low latency. C++ based cycle level implementation of the proposed architecture, sparse Finite Impulse Response filtering application analysis and measurement results from the testchip in 28nm CMOS validate the proposed autonomous distributed control. Finally, the thesis considers a larger scale design of the proposed distributed control and discusses its end-to-end implementation in 28nm CMOS along with simulation results.