The objective of the proposed research is to develop a signal-chain optimized Noise-Shaping (NS) Successive-approximation-register (SAR) analog-to-digital converter (ADC) with low power consumption and high resolution. Noise-shaping (NS) SAR ADC, which inherits the advantage of SAR ADCs and Delta-Sigma ADCs, is being considered the next-generation high-performance ADC for both academy and the industry. It adopts SAR ADC as a quantizer and utilizes the noise shaping feature to achieve high resolution in an efficient way. With NS SAR ADCs, the low-power analog front end can be designed but the input driving buffer in the signal chain becomes the new bottleneck of system performance. This proposal aims to co-design the components in signal chain with NS SAR ADC to get optimized system performance. As preliminary research, an input driving buffer embedded NS SAR ADC has been designed and taped out. It successfully reduces input driving requirements and achieves state-of-the-art performance. In future work, the design of the dynamic amplifier-in-loop based NS SAR ADC is in progress which integrates both amplifier and buffer with NS SAR ADC to further reduce the power and suppress the noise. The outcome of the proposed research will benefit edge devices to finish high-precision tasks with extended battery life. This will support electronic engineers in both academia and industry to achieve a high-performance AFE design at a low cost.