dvanced data-intensive computing models that go beyond conventional von-Neumann architectures require memory technologies that can offer high-density and low-power capabilities, exceeding the performance of current flash memory. ferroelectric field effect transistors (FEFETs) are one of such emerging memory technologies. Since the discovery of ferroelectricity in binary oxides based on hafnia and zirconia, which are complimentary metal-oxide-semiconductor (CMOS) compatible, there has been a renewed scientific interest in FEFETs for advanced electronic memory applications in mainstream high-volume manufacturing platforms. Although FEFETs exhibit low write energy, ultra-fast read and write speeds, and compact device size, they face several challenges to be integrated into the embedded memory applications. The objective of this dissertation is to conduct experiments to gain a better understanding of the device physics of the FEFET. The intuition obtained from these experiments can be leveraged to update the FEFET’s gate design for its integration in embedded platforms and advanced technology nodes. Furthermore, the extensive experimental data collected in this work can be used to develop a predictive compact model of FEFETs that accounts for the trapping effects observed in these devices. By following the guidelines outlined in this work, further trap analysis can be conducted to refine this model. Ultimately, this work can provide valuable insights to engineers seeking to design processes to optimize the gate-stack of an FEFET and improve its performance as a non-volatile memory element.