PhD Proposal by Pragna Bhaskar

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Under the provisions of the regulations for the degree 


on Friday, June 24, 2022

9:30 AM

in Pettit Microelectronics Building – 102A


and via


Zoom Videoconferencing



will be held the


Pragna Bhaskar

"Reliability Assessment of Ultra-low-k Dielectric Materials and Demonstration in Advanced Interposers"

Committee Members:

Prof. Madhavan Swaminathan, Co-advisor, ECE/MSE

Prof. Mark D. Losego, Co-advisor, MSE

Mohanalingam Kathaperumal, PhD, ECE

Prof. Hamid Garmestani, MSE

Prof. Preet Singh, MSE




The number of connected devices in homes, cars and offices has increased and there is also an increase in advanced data processing algorithms. These have been enabled by artificial intelligence (AI) unprecedented need for ultra-high bandwidth computing. This need for ultra-high bandwidth is driving transistor density on single-chips. Moore’s Law has enabled the scaling and integration of compute, memory, and other functionalities on a single silicon chip by increasing transistor density on-chip at lower cost per transistor. This is known as System on Chip (SoC) approach.


In the recent past, Moore’s law has slowed down and the cost of large SoCs has increased. There are two important reasons for this exponential increase in cost. The first reason is that the cost/mm2 of transistors has continued to increase due to increase in technology complexity. The second reason is that yields have reduced for larger SoCs as the limits of the reticle field are approached. One of the methods to address these requirements is by adopting Heterogeneous Integration. In this approach, separately manufactured dies are integrated onto an advanced interposer which provides better functionality and operating characteristics.


These dies need to communicate with high bandwidth density at low energy per bit (EPB). Bandwidth density depends on wiring density, wire length, and signaling data rate on each wire. Signal speed is determined primarily by the dielectric constant. Low wire capacitance can be achieved by shorter wires between dies and low dielectric constant materials. Therefore, there is need for integration of ultra-low k materials in the redistribution wiring layers (RDLs) of the package. Earlier studies involved materials having dielectric constant in the range of 2.65 to 3.2.


It has been reported that when the dielectric constant (k) is reduced from 3.9 to 2.4, the EPB is reduced by 40%. Therefore, the present study proposes to study ultra-low-k dielectric materials which have dielectric constant in the range of 2.1 to 2.4. This study proposes to perform the electrical characterization of these materials by evaluating dielectric constants in the range of 10-170 GHz and measuring the insertion losses. Typically, the ultra-low-k materials have inert chemistries and there is a possibility of lower adhesion to metal layers. Therefore, there is a need to study chemical reliability. This study involves improving the adhesion between dielectric and metal layer. Another aspect of chemical reliability is moisture absorption. This is evaluated by comparing the behavior of these materials before and after highly accelerated stress test (HAST). For the ultra-low-k materials to be suitable for use in RDL having high wiring density, there is need to demonstrate fine line features and formation of vias. Therefore, fabrication of fine line features <5 µm and microvias <10 µm will be demonstrated on these materials. In addition, different methods to measure the coefficient of thermal expansion (CTE) of these thin polymer dielectric films and methods to reduce CTE will be evaluated.


  • Workflow Status:Published
  • Created By:Tatianna Richardson
  • Created:06/13/2022
  • Modified By:Tatianna Richardson
  • Modified:06/13/2022